EC8552 Computer Architecture and Organization Notes
EC8552 NOTES Computer Architecture and Organization MCQ for ece 5th semester as well as the cse students notes with the real time example and very simple to understand to get more marks in cao.
Anna University 2017 regulation and 2021 regulation for electronics and communication engineering is subject name is computer architecture and organization this is one of the most important paper related to computer science department this paper is contains totally 5 units.
Overview of syllabus EC8552 Computer Architecture and Organization
Unit 1 is computer organization and instruction all the basic questions contains in unit 1 the eight ideas of computer architecture and organization, the performance of computer the power of computer architecture, what is uniprocessor, what is multi process, what is addressing modes, what are the types of addressing modes in computer architecture and organization, all the basic concepts contains in unit 1.
the main important is instructions, what is instructions in computer architecture, what are the types of instructions logical operation control operation contains in unit 1.
You need to is study about arithmetic operation this unit contains all type of computer based problems it’s like addition subtraction multiplication and division this each and every problems having different methods, one of the most important questions frequently asked University point of view is restoring problem and non restoring problem is one of the most important question in this unit 2 if you study the two question definitely you will get 10 marks in your university point of view, so you need to study that to that questions.
Computer architecture and organization important multiple choice questions and answers given in below video if you refer that video you definitely clear your computer architecture and organization because all the important questions given above video the Anna University online examination point of view all the important questions and answers I explained with the real examples so students can understand easily all the five unit important multiple choice questions and answers I explained in the above video.
UNIT 1
COMPUTER ORGANIZATION AND INSTRUCTIONS
i) EIGHT IDEAS
- 1 DESIGN FOR MOORE’S LAW
- 2 USE ABSTRACTION TO SIMPLIFY DESIGN
- 3 MAKE THE COMMON CASE FAST
- 4 PERFORMANCE VIA PARALLEISM
- 5 PERFORMANCE VIA PIPELING
- 6 PERFORMANCE VIA PREDICTION
- 7 HIERARCHY OF MEMORIES
- 8 DEPENDABILITY VIA REDUNDANCY
1 DESIGN FOR MOORE’S LAW:
The MOORE’S LAW in computer architecture STATES THAT INTEGRATED CIRCUIT that ic RESOURECES DOUBLE 18-24 MONTHS.
the main of moor’s law is ACCORDING TO MOORE’S LAW COMPUTER ARCHITECTS MUST KNOW WHERE THE TECHNOLOGY IS GOING AND WHEN THE DESIGN HAS TO FINISH.
2 USE ABSTRACTION TO SIMPLIFY DESIGN
IT HELPS TO REDUCE THE DESIGN TIME OF BOTH COMPUTER ARCHITECTURE AND PROGRAMMES
3 MAKE THE COMMON CASE FAST
COMPUTER ARCHITECTURE FUNCION OF COMMON CASE AND RARE CASE IS THE METHOD.
COMMON CASE FAST WILL PERFORMANCE BETTER THAN OPTIMIZING THE RARE CASE
COMMON CASE IS SIMPLES THAN THE RARE CASE SO IT IS EASIER TO ENHACE.
4 PERFORMANCE VIA PARALLELISM
PERFORMANCE OF COMPUTER CAN BE INCREASED BY PARALLELISM BECAUSE PARALLEL PROCESSING WITH INCREASE THE SPEED OF PERFORMANCE EXECUTION.
COMPUTER ARCHITECTURE DESIGN HAS MORE PERFORMANCE BY PERFORMING OPERATIONS IN PARALLEL
5 PERFORMANCE VIA PIPELING
PARALLALISM CAN BE PERFORMED IN MANY WAYS. IT CAN BE ACHIEVIED BY CONCEPT OF PIPELING
6 PERFORMANCE VIA PREDICTION
COMPUTER ARCHITECTURE WILL IMPROVE SYSTEM PERFORMANCE.
7 HIERARCHY OF MEMORIES
MEMORY IS MOST IMPORTANT PARTS IN COMPUTER.
8 DEPENDABILITY VIA REDUNANCY
COMPUTER ARE NEED TO BE FAST AS WELL DEPENDABLE COMPUTER CONTANIS COLLECTION OF PHYSICAL DEVICES.
II) COMPONENTS OF COMPUTER SYSTEM
COMPUTER HARDWARE CAN BE CLASSIFIED INTO MANY UNITS
1 INPUT UNIT
2 OUTPUT UNIT
PROCESSING UNITS IN COMPUTER
ALU UNIT
CONTROL UNIT
MEMORY
INPUT UNITS
WHENEVER A KEY IS PRESED, THE CORRESPONDING LETTER OR DIGIT IS AUTOMATICALLY TRANSLATES INTO ITS CORROSPONDING BINARY CODE..
EG — KEYBOARD MOUSE
2 OUTPUT UNIT
THE OUTPUT CAN BE OBTAINED IN TWO FORM
HARDCOPY AND SOFYCOPY
THE PHYSICAL FORM OF THE OUTPUT IS CALLED HARD
EG MONITORS.
3 CENTRAL PROCESSING UNIT(CPU)
IT CONSITS OF THREE PARTS
i ALU ARITHMETIC AND LOGIC UNIT
ii CONTROL UNIT
iii REGISTER
THE ARITHMETIC OPERATION SUCH AS ADDITION
SUBTRACTION
,DIVISION,
MULTIPILCATION
AND LOGICAL OPERATIONS
SUCH AS EQUAL TO.
GREATER THAN,
LESS THEN ,
AND ,OR FUNCTIONS
CONTROL UNIT
CONTROL UNIT IS A PART OF THE HARDWARE.
IT DIRECTS THE COMPUTER SYSTEM TO EXECUTE
REGISTERS
A SMALL TEMPORARY STORAGE UNIT IS CALLED REGISTERS.
TWO TYPES OF REGISERS
i GENERAL PURPOSE REGISTERS (GPR)
ii SPECIAL PURPOSE REGISTER (SPR)
SPECIAL PURPOSE REGISTERS
SOME OF SPECIFIC PURPOSE REGISTERS ARE
i MEMORY ADDRESS REGISTER (MAR)
ii MEMORY DATA REGISTER (MDR)
iii INSTRUCTION REGISTER (IR)
iv PROGRAM COUNTER (PC)
v ACCUMULATOR
THE ADDRESS OF THE OPERAND WHICH IS TO BE FETCH FROM MEMORY
IT IS UNIDIRECTIONAL
IT ONLY SENDS ADDRESS TO MEMORY
MDR HOLDS DATA WHICH IS STORED OR RECEIVED FROM OR TO MEMORY.
IT IS BIDIRECTIONAL
IT IS ALSO CALLED BUFFER REGISTER
PROGRAM COUNTER (PC)
Register holds the address.
INSTRUCTION REGISTER
IR HOLDS THE CURRENT INSTRUCTION THAT IS FETCHED.
4 MEMORY UNIT
MEMORY IS MAINLY CLASSIFIED INTO TWO CATEGORIES
i PRIMARY MEMORY (ram and rom)
ii SECONDARY MEMORY (cache)
PRIMARY MEMORY
IT IS KNOWN AS A MAIN MEMORY – —- IN BUILT MEMORY
IT STORES DATA ADN INSTURCTIONS FOR PROCESSING
MEMORY CONTAINS LARGE NUMBER OF SEMICONDUCTOR STORAGE CELLS
EACH CELL CARRIES 1 BIT OF INFORMATION
RAM IS A VOLATILE MEMORY (ie) THE CONTENTS ARE LOST WHEN THE DEVICE IS POWERED OFF
TYPES OF ROM ARE PROM, EPROM,, EEPROM,,
SECONDARY MEMORY
IT ALSO KNOWN AS AUXILIARY MEMORY AND EXTERNAL MEMORY
IT IS HIGH EXPENSIVE AND SMALL IN SIZE
IT IS PRESENT IS TWO OR THREE FORMS IN A SYSYEM L1,L2,L3 CACHE MEMORIES
3 INSTRUCTIONS of EC8552 Computer Architecture and Organization
THE WORD’S OF COMPUTER’S LANGUAGE ARE CALLED INSTRUCTIONS AND ITS VOCABULARY IS CALLED INSTRUCTION SET
INSTRICTION SET WILL DESCRIBE THE FUNCTIONS OF ARCHITECTURE
THREE POPULAR INSTRUCTION SETS ARE
ARM V7 SIMILAR TO MIPS TECHNOLOGIES
A BILLION CHIPS WITH ARM PROCSSOR
INTEL x86 POWER BOTH THE PC AND CLOUD
EG ARITHMETIC INSTRUCTIONS
LOGIC INSTRUCTIONS
CONTROL FLOW INSTRUCTIONS
DATA HANDLING AND MEMORY INSTRUCTIONS
AN INSTRUCTION HAS THREE FIELDS
OPERATION CODE (OPCODE) SPECIFY TYPE OF OPERATION
MODE FIELD SPECIFY THE WAY OF OPERAND AND EFFIECTIVE ADDRESS
ADDRESS FILED SPECIFIES MEMORY ADDRESS OR A PROCESSOR REGISTER
OPCODE
MODE FIELD
ADDRESS FIELD
O OPERAND INSTRUCTION OR ZERO ADDRESS INSTRUCTION.
EG PUSH A
ONE ADDRESS INSTRUCION
ADD A THE VALUE OF A IS ADDED WITH ACCUMULATOR CONTENT
LOAD A
STORE A
TWO ADDRESS INSTURCION
THREE ADDRESS INSTRUCIONS
MIPS INSTRUCTION FORMATS
R FORMAT
FIELD BITPOSITION
OPCODE 31 TO 26
RS 25 TO 21
RT 20 TO 16
RD 15 TO 11
SHAMT 10 TO 6
FUNCT 5 TO 0
THREE REGISTER OPERANDS RS, RT, AND RD
RS AND RT = SORUCES
RD = DESTINATION
SHAMT FIELD = USED ONLY FOR SHIFTS
FUNCTION FIELD = THE ALU FUCTIONS
I FORMAT
FIELD BITPOSITION
OPCODE 31 TO 26
RS 25 TO 21
RT 20 TO 16
ADDRESS 15 TO 0
FOR LOAD AND STORE INSTRUCTIONS
OPCODE = 35 FOR LOAD AND
OPCODE =43 FOR STORE
RS = THE BASE REGISTER
FOR BRANCH INSTURCIONS
OPCODE 4
J FORMAT
FEILD BITPOSITION
OPCODE 31 TO 26
ADDRESS 25 TO 0
THE DESTINATION ADDRESS IS COMPUTED AS
EG JAL R1
JUMP AND LINK
CAO UNIT 2
RESTORING DIVISION
REMAINDER= DIVISOR+ SET Q
00011
00001
remainder=00100
NON RESTORING DIVISION
REMAINDER=DIVISOR+SET Q
00011
00001
remainder=00100
UNIT 1
ADDRESSING MODES
OPERAND
OPERATOR
2+2 = 4
2 IS OPERAND
+ is operator
a+b =c
a,b IS THE OPERANDS
+ IS THE OPERATOR
+ – * / = OPERATORS
a,b,c = OPERANDS
ADDRESSING MODES of EC8552 Computer Architecture and Organization
1. IMMEDIATE ADDRESSING
2.REGISTER ADDRESSING
3.BASE ADDRESSING
4.PC RELATIVE ADDRESSING
5.PSEUDO DIRECT ADDRESSING
op = operand
opcode =operation code
rs = source register
rt = source register
rd = destination register
funct = function
b = byte
hw = half word
w = word
PC = PROGRAM COUNTER
1.IMMEDIATTE ADDRESSING =NUMERIC VALUES
2.REGISTER ADDRESSING =LIMIT VALUES
3.BASE ADDRESSING = REGISTER = BYTE
4.PC RELATIVE = MEMORY = WORD =PROGRAM COUNTER
5.PSEUDO DIRECT = DATA
1. IMMEDIATE ADDRESSING
op rs rt IMMEDIATE
2. REGISTER ADDRESSING
op rs rt rd……. funct REGISTER
3. BASE ADDRESSING
op rs rt address MEMORY
REGISTER BYTE
HALF WORD
WORD
4. PC RELATEIVE ADDRESSING
op rs rt …addresss MEMORY
pc WORD
5. PSEUDO DIRECT ADDRESSING
op address MEMORY
pc WORD
UNIT 1 IMPORTANT QUESTION
EC8552
COMPUTER ARCHITECTURE AND ORGANIZATION
UNIT 1
COMPUTER ORGANIZATION AND INSTRUCTION
1. EIGHT IDEAS
2. COMPONENTS OF COMPUTER SYSTEM
3.INSTRUCTIONS
4. ADDRESSING MODES
UNIT 5
FLYNN’S CLASSIFICATION
1 MULTIPROCESSOR
2 MULTIPROCESSING
3 PARALLE ARCHITECTURE
SISD
SIMD
MISD
MIMD
CLASSIFICATION
FLYNN’S TAXONOMY
SISD
SIMD
MISD
MIMD
UMA – UNIFORM MEMORY ACCESS
SHARED MEMORY MULTIPROCESSOR
SMP- SYMMETRIC MULTI PROCESSOR
PROCESSOR
CACHE
MAIN MEMORY
I/O SYSTEM
PHYSICALLY DISTRIBUTED MEMORY MULTIPROCESSOR
PROCESSOR + CACHE
MEMORY I/O
INTERCONNECTION NETWORK
MEMORY I/O
PROCESSOR+CACHE
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